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| 74ACT138 Datasheet, PDF (1/10 Pages) STMicroelectronics – 3 TO 8 LINE DECODER INVERTING | |||
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74ACT138
3 TO 8 LINE DECODER (INVERTING)
s HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.)
s 50⦠TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH â
tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 138
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT138 is an advanced high-speed CMOS
3 TO 8 LINE DECODER (INVERTING) fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS tecnology.
If the device is enabled, 3 binary select inputs (A,
B, and C) determine which one of the outputs will
go low. If enable input G1 is held low or either G2A
or G2B is held high, the decoding function is
inhibited and all the 8 outputs go to high.
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT138B
74ACT138M
T&R
74ACT138MTR
74ACT138TTR
Three enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/10
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