74ACT1284 Datasheet, PDF (1/11 Pages) Fairchild Semiconductor – IEEE 1284 Transceiver

74ACT1284
HIGH SPEED IEEE1284 TRANSCEIVER
s HIGH SPEED:
T_PD = 6.5 ns (Max. 85°C) at V_CC = 4.5V
s LOW POWER DISSIPATION:
I_CC = 80 µA (MAX.) at V_CC = 5.5V T = 85 °C
s TTL COMPATIBLE INPUTS
V_IH = 2V (Min.) V_IL = 0.8V (Max.)
s OPERATING VOLTAGE RANGE:
V_CC (OPR.) = 4.5V to 5.5V
s A Port have standard 4mA totem pole output
s B Port high drive source/sink capability of
14mA
s Support IEEE Std 1284-I (level 1 type) and
IEEE Std 1284-II (level 2 type) for bidirectional
parallel communications between personal
computer and printing peripherals.
DESCRIPTION
The 74ACT1284 contains four high-speed non-in-
verting bidirectional buffers and three non-invert-
ing buffers with open drain outputs fabricated in
silicon gate C²MOS technology.
It’s intended to provide a standard signaling meth-
od for a bidirection parallel peripheral in an Ex-
tended Capabilities Port mode (ECP).
The HD (active High) input pin enables the B ports
to switch from Open Drain to a high drive totem
pole output, capable of sourcing 14mA on all sev-
en buffers. The DIR input determines the direction
of data flow on the bidirectional buffers.
DIR (active High) enables data flow from A Port to
B Port. DIR (active Low) enables data flow from B
Port to A Port.
ESD protection is greater than 2000V per Method
3015.7 of MIL-STD-883B. It’s available in the
commercial temperature ranges.
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
SOP
TSSOP
74ACT1284M
T&R
74ACT1284MTR
74ACT1284TTR
PIN CONNECTION
July 2003
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