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| 74ACT125MTR Datasheet, PDF (1/9 Pages) STMicroelectronics – QUAD BUS BUFFERS (3-STATE) | |||
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74ACT125
QUAD BUS BUFFERS (3-STATE)
s HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.)
s 50⦠TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH â
tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 125
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74ACT125 is an advanced high-speed CMOS
QUAD BUS BUFFER fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology.
This device require the 3-STATE control input G to
be set high to place the output in high impedance
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT125B
74ACT125M
T&R
74ACT125MTR
74ACT125TTR
state.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/9
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