74ACT11 Datasheet, PDF (1/7 Pages) STMicroelectronics – TRIPLE 3-INPUT AND GATE

74ACT11
TRIPLE 3-INPUT AND GATE
s HIGH SPEED: t_PD = 6.5 ns (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 4 µA (MAX.) at T_A = 25 ^oC
s COMPATIBLE WITH TTL OUTPUTS
V_IH = 2V (MIN), V_IL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 11
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT11 is an advanced high-speed CMOS
TRIPLE 3-INPUT AND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C²MOS technology. It is ideal for low
power applications mantaining high speed
PRELIMINARY DATA
B
M
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT11B
74ACT11M
operation similar to equivalent Bipolar Schottky
TTL.
The internal circuit is composed of 4 stages
including buffer output, which enables high noise
immunity and stable output.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1997
1/7