74AC74MTR Datasheet, PDF (1/12 Pages) STMicroelectronics – DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

74AC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
f_MAX = 300MHz (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 2µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN)
s BALANCED PROPAGATION DELAYS:
t_PLH ≅ t_PHL
s OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C²MOS tecnology.
A signal on the D INPUT is transferred to the Q
and Q OUTPUTS during the positive going
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC74B
74AC74M
T&R
74AC74MTR
74AC74TTR
transition of the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
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