74AC16373 Datasheet, PDF (1/10 Pages) STMicroelectronics – IMPROVED LATCH-UP IMMUNITY

74AC16373
16-BIT D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS (NON INVERTED)
s HIGH SPEED:
t_PD = 5.0 ns (TYP.) at V_CC = 5V
s LOW POWER DISSIPATION:
I_CC = 8µA(MAX.) at T_A=25°C
s HIGH NOISE IMMUNITY:
V_NIH = V_NIL = 28 % V_CC (MIN.)
s 50Ω TRASMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|I_OH| = I_OL = 24mA (MIN)
s OPERATING VOLTAGE RANGE:
V_CC (OPR) = 2V to 6V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74AC16373 CMOS 16 BIT D-TYPE LATCH
with 3 STATE OUTPUTS NON INVERTING
fabricated with sub-micron silicon gate and
double-layer metal wiring C²MOS technology.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(nOE).
While the nLE input is held at a high level, the nQ
outputs will follow the data (D) inputs.
When the nLE is taken LOW, the nQ outputs will
be latched at the logic level of D data inputs.
When the (nOE) input is low, the nQ outputs will
be in a normal logic state (high or low logic level);
when nOE is at high level ,the outputs will be in a
high impedance state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
PIN CONNECTION
T&R
74AC16373TTR
February 2003
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