English
Language : 

54VCXH162374_11 Datasheet, PDF (1/18 Pages) STMicroelectronics – Rad hard low voltage CMOS 16-bit d-type flip-flop (3-state) with 3.6 V tolerant inputs and outputs
54VCXH162374
Rad hard low voltage CMOS 16-bit d-type flip-flop (3-state)
with 3.6 V tolerant inputs and outputs
Features
■ 1.65 to 3.6 V inputs and outputs
■ High speed:
– tPD = 3.4 ns (Max.) at VCC = 3.0 to 3.6 V
– tPD = 4.8 ns (Max.) at VCC = 2.3 to 2.7 V
■ Symmetrical impedance outputs:
– |IOH| = IOL = 12 mA (Min.) at VCC = 3.0 V
– |IOH| = IOL = 8 mA (Min.) at VCC = 2.3 V
■ Power down protection on inputs and outputs
■ 26 Ω serie resistors in outputs
■ Operating voltage range:
– VCC(Opr) = 1.65 V to 3.6 V
■ Pin and function compatible with 54 series
H162374
■ Bus hold provided on both sides
■ Cold spare function
■ Latch-up performance exceeds
300 mA (JESD 17)
■ ESD performance:
– HBM > 2000 V
(MIL STD 883 method 3015); MM > 200 V
■ 300 KRad Mil1019.6 condition A, (RHA QML
qualification extension undergone)
■ No SEL, no SEU and no SET under 110
Mev/cm2/mg LET heavy ions irradiation
■ QML qualified product
■ Device fully compliant with
DSCC SMD 5962-05212
■ 100 mV typical input hysteresis
Flat-48
The upper metallic lid is not electrically connected to any
pins, nor to the IC die inside the package.
Description
The 54VCXH162374 is a low voltage CMOS 16
bit d-type flip-flop with 3 state outputs non
inverting fabricated with sub-micron silicon gate
and five-layer metal wiring C²MOS technology. It
is ideal for low power and very high speed 1.65 to
3.6 V applications; it can be interfaced to 3.6 V
signal environment for both inputs and outputs.
These 16 bit d-type flip-flops are controlled by two
clock inputs (nCK) and two output enable inputs
(nOE). On the positive transition of the (nCK), the
nQ outputs will be set to the logic state that were
setup at the nD inputs. While the (nOE) input is
low, the 8 outputs (nQ) will be in a normal state
(HIGH or LOW logic level) and while high level the
outputs will be in a high impedance state. Any
output control does not affect the internal
operation of flip flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are OFF.
August 2011
Doc ID 10654 Rev 7
1/18
www.st.com
18