54VCXH162244_11 Datasheet, PDF (1/18 Pages) STMicroelectronics – Low voltage CMOS 16-bit bus buffer (3-state non inverter) with 3.6 V tolerant inputs and outputs

54VCXH162244
Low voltage CMOS 16-bit bus buffer (3-state non inverter)
with 3.6 V tolerant inputs and outputs
Features
■ 1.65 to 3.6 V inputs and outputs
■ High speed:
– t_PD = 3.4 ns at V_CC = 3.0 to 3.6 V
– t_PD = 3.8 ns at V_CC = 2.3 to 2.7 V
■ Power down protection on inputs and outputs
■ Symmetrical output impedance:
– |I_OH| = I_OL = 12 mA (Min.) at V_CC = 3.0 V
– |I_OH| = I_OL = 8 mA (Min.) at V_CC = 2.3 V
■ 26 Ω serie resistors in outputs
■ Operating voltage range:
– V_CC(Opr) = 1.65 V to 3.6 V
■ Pin and function compatible with 54 series
H162244
■ Bus hold provided on data inputs
■ Cold spare function
■ Latch-up performance exceeds
300 mA (JESD 17)
■ ESD performance:
– HBM > 2000 V
(Mil Std 883 Method 3015); MM > 200 V
■ 300 krad Mil1019.6 condition A, (RHA QML
qualification extension undergone)
■ No SEL, no SEU and no SET under 110
Mev/cm2/mg LET heavy ions irradiation
■ QML qualified product
■ SMD 5962-05210
■ 100 mV typical input hysteresis
Flat-48
The upper metallic lid is not electrically connected to any
pins, nor to the IC die inside the package.
Description
The 54VCXH162244 is a low voltage CMOS 16
bit bus buffer (non inverted) fabricated with sub-
micron silicon gate and five-layer metal wiring
C²MOS technology. It is ideal for low power and
very high speed 1.65 to 3.6 V applications; it can
be interfaced to 3.6 V signal environment for both
inputs and outputs. Any nG output control
governs four BUS buffers. Output enable input
(nG) tied together gives full 16-bit operation.
When nG is low, the outputs are on. When nG is
high, the output are in high impedance state. This
device is designed to be used with 3 state
memory address drivers, etc. Bus hold on data
inputs is provided in order to eliminate the need
for external pull-up or pull-down resistor. The
device circuits is including 26 Ω series resistance
in the outputs. These resistors permit to reduce
line noise in high speed applications. All inputs
and outputs are equipped with protection circuits
against static discharge, giving them 2 kV ESD
immunity and transient excess voltage.
July 2011
Doc ID 10652 Rev 9
1/18
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