486DX Datasheet, PDF (1/8 Pages) STMicroelectronics – ST 486 DX ASIC CORE

ST 486 DX ASIC CORE
Fully Static 3.3V 486 DX/DX2/DX4 ASIC CORE
PRELIMINARY DATA
s Fully Static 486 compatible core able to
operate from D.C to 120MHz
s Manufactured in a 0.35 micron five layer
metal HCMOS process
s 8K byte unified instruction and data cache
with write back capability
s Parallel processing integral floating point unit,
with automatic power down mode
s Low Power system management modes
s Cell libraries for 2.2V and 3.3V supply with
5 V I/O interface capability
s 2 - input NAND delay of 0.160 ns (typ) with
fanout = 2.
s Broad I/O functionality including LVCMOS,
LVTTL, GTL, PECL, and LVDS.
s High drive I/O; capability of sinking up to 48
mA with slew rate control, current spike sup-
pression and impedance matching.
s Generators to support SPRAM, DPRAM,
ROM and many other embedded functions.
s Fully independent power and ground configu-
rations for inputs, core and outputs.
s Programmable I/O ring capability up to 1000
pads.
s Output buffers capable of driving ISA, EISA,
PCI, MCA, and SCSI interface levels.
s Active pull up and pull down devices.
s Buskeeper I/O functions.
s Oscillators for wide frequency spectrum.
s Broad range of 400 SSI cells.
s Design For Test includes LSSD macro library
option and IEEE 1149.1 JTAG Boundary
Scan architecture built in.
s Cadence based design system with inter-
faces from multiple workstations.
s Broad ceramic and plastic package range.
s Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts.
Figure 1. Example 486 DX Core ASIC
S e a o f G at e s
Stand ard C ells
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C H IPSE T / PC I
ID E / ISA
SV G A
486
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C us tom I/O
e .g R A M D A C
Prog ram m able
I/O
October 1995
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