ST2309ES Datasheet, PDF (1/8 Pages) Stanson Technology – SOT-23 package design

ST2309ES
P Channel Enhancement Mode MOSFET
-3.0A
DESCRIPTION
ST2309ES is the P-Channel logic enhancement mode power field effect transistor
which is produced using high cell density, DMOS trench technology. This high density
process is especially tailored to minimize on-state resistance. These devices are
particularly suited for low voltage application such as cellular phone and notebook
computer power management, other battery powered circuits, and low in-line power
loss are required. The product is in a very small outline surface mount package.
PIN CONFIGURATION
SOT-23
3
D
G
S
1
2
FEATURE
! -60V/-3.0A, R_DS(ON) = 160m-ohm
@VGS = -10V
! -60V/-1.5A, R_DS(ON) = 200m-ohm
@VGS = -4.5V
! Super high density cell design for
extremely low R_DS(ON)
! Exceptional on-resistance and maximum
DC current capability
! SOT-23 package design
1.Gate 2.Source 3.Drain
PART MARKING
SOT-23
3
21YA
1
2
Y: Year Code A: Process Code
STANSON TECHNOLOGY
120 Bentley Square, Mountain View, Ca 94040 USA
www.stansontech.com
ST2309ES 2015. Rev.1