SST49LF040 Datasheet, PDF (8/48 Pages) Silicon Storage Technology, Inc – 4 Mbit LPC Flash

4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 1: PIN DESCRIPTION
Symbol
A₁₀-A₀
Pin Name
Address
DQ₇-DQ₀ Data
OE#
WE#
MODE
Output Enable
Write Enable
Interface
Mode Select
INIT#
Initialize
ID[3:0]
or
ID[3:1]
GPI[4:0]
Identification
Inputs
General
Purpose Inputs
TBL#
Top Block Lock
LAD[3:0] Address and
Data
LCLK
Clock
LFRAME# Frame
RST#
WP#
Reset
Write Protect
R/C#
RES
V_DD
V_SS
CE#
Row/Column
Select
Reserved
Power Supply
Ground
Chip Enable
NC
No Connection
1. I=Input, O=Output
Type¹
I
I/O
I
I
I
I
I
I
I
I/O
I
I
I
I
I
PWR
PWR
I
I
Interface
PP LPC
X
X
X
X
XX
X
X
X
X
X
X
X
XX
X
X
X
XX
XX
X
XX
Functions
Inputs for low-order addresses during Read and Write operations. Addresses are
internally latched during a Write cycle. For the programming interface, these
addresses are latched by R/C# and share the same pins as the high-order
address inputs.
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# is high.
To gate the data output buffers.
To control the Write operations.
This pin determines which interface is operational. When held high, programmer
mode is enabled and when held low, LPC mode is enabled. This pin must be
setup at power-up or before return from reset and not change during device oper-
ation. This pin must be held high (V_IH) for PP mode and low (V_IL) for LPC mode.
This is the second reset pin for in-system use. This pin is internally combined
with the RST# pin; If this pin or RST# pin is driven low, identical operation is
exhibited.
These four pins are part of the mechanism that allows multiple parts to be attached
to the same bus. These pins are internally pulled-down with a resistor between 20-
100 KΩ
These individual inputs can be used for additional board flexibility. The state of
these pins can be read through LPC registers. These inputs should be at their
desired state before the start of the PCI clock cycle during which the read is
attempted, and should remain in place until the end of the Read cycle. Unused
GPI pins must not be floated.
When low, prevents programming to the boot block sectors at top of memory.
When TBL# is high it disables hardware write protection for the top block sectors.
This pin cannot be left unconnected.
To provide LPC control signals, as well as addresses and Command
Inputs/Outputs data.
To provide a clock input to the control unit
To indicate start of a data transfer operation; also used to abort an LPC cycle
in progress.
To reset the operation of the device
When low, prevents programming to all but the highest addressable blocks.
When WP# is high it disables hardware write protection for these blocks.
This pin cannot be left unconnected.
Select for the Programming interface, this pin determines whether the address
pins are pointing to the row addresses, or to the column addresses.
These pins must be left unconnected.
To provide power supply (3.0-3.6V)
Circuit ground (0V reference)
This signal must be asserted to select the device. When CE# is low, the device
is enabled. CE# must remain low during internal Write (Program or Erase)
operations. When CE# is high, the device is placed in low power Standby mode.
Unconnected pins.
T1.4 562
©2001 Silicon Storage Technology, Inc.
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