SST34HF32A4 Datasheet, PDF (7/37 Pages) Silicon Storage Technology, Inc – 32 Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory

32 Mbit Concurrent SuperFlash + 16 Mbit PSRAM ComboMemory
SST34HF32A4
Preliminary Specifications
PSRAM Operation
With BES1# low, BES2 and BEF# high, the
SST34HF32A4 operate as 1024K x16 CMOS PSRAM,
with fully static operation requiring no external clocks or tim-
ing strobes. The SST34HF32A4 PSRAM is mapped into
the first 1024 KWord address space. When BES1#, BEF#
are high and BES2 is low, all memory banks are dese-
lected and the device enters standby. Read and Write cycle
times are equal. The control signals UBS# and LBS# pro-
vide access to the upper data byte and lower data byte.
See Table 5 for Read and Write data byte control modes of
operation.
PSRAM Deep Power-Down Mode
This mode can be used to lower the power consumption of
the PSRAM in the SST34HF32A4 device only. Deep
power-down occurs 1µs after being enabled by driving
BES2 low. Normal operation occurs 500µs after BES2 is
driven high. In deep power-down mode, PSRAM data is
lost.For details, see Figure 1.
PSRAM Read
The PSRAM Read operation of the SST34HF32A4 is con-
trolled by OE# and BES1#, both have to be low with WE#
and BES2 high for the system to obtain data from the out-
puts. BES1# and BES2 are used for PSRAM bank selec-
tion. OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when OE# is high. Refer to the Read cycle timing diagram,
Figure 5, for further details.
PSRAM Write
The PSRAM Write operation of the SST34HF32A4 is con-
trolled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the PSRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagrams, Figures 6 and 7, for further details.
Power-up
Sequence
Power on
BES1# = VIH or
VIL, BES2 = VIH
Initial State
(Wait 200 µs)
Deep
Power-down
Exit
Sequence
BES1# = VIH or
VIL, BES2 = VIH
Active
BES2 = VIL
BES2 = VIH,
BES1# = VIL,
LBS# = VIH,
BES2 = VIH,
BES1# = VIH or UBS# UBS# & LBS# and/or LBS# = V_IL
Deep
Power-down
Mode
BES2 = VIL
FIGURE 1: Deep Power-Down State Diagram
Standby
Mode
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©2006 Silicon Storage Technology, Inc.
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