SST25VF040B Datasheet, PDF (7/28 Pages) Silicon Storage Technology, Inc – 4 Mbit SPI Serial Flash

4 Mbit SPI Serial Flash
SST25VF040B
Block Protection (BP3,BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
size of the memory area, as defined in Table 4, to be soft-
ware protected against any memory Write (Program or
Erase) operation. The Write-Status-Register (WRSR)
instruction is used to program the BP3, BP2, BP1 and BP0
bits as long as WP# is high or the Block-Protect-Lock
(BPL) bit is 0. Chip-Erase can only be executed if Block-
Protection bits are all 0. After power-up, BP3, BP2, BP1
and BP0 are set to 1.
Data Sheet
Block Protection Lock-Down (BPL)
WP# pin driven low (V_IL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.
When the WP# pin is driven high (V_IH), the BPL bit has no
effect and its value is “Don’t Care”. After power-up, the BPL
bit is reset to 0.
TABLE 4: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF040B¹
Status Register Bit²
Protected Memory Address
Protection Level
BP3
BP2
BP1
BP0
4 Mbit
None
X
0
0
0
None
Upper 1/8
X
0
0
1
70000H-7FFFFH
Upper 1/4
X
0
1
0
60000H-7FFFFH
Upper 1/2
X
0
1
1
40000H-7FFFFH
All Blocks
X
1
0
0
00000H-7FFFFH
All Blocks
X
1
0
1
00000H-7FFFFH
All Blocks
X
1
1
0
00000H-7FFFFH
All Blocks
X
1
1
1
00000H-7FFFFH
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
T4.0 1295
©2006 Silicon Storage Technology, Inc.
7
S71295-01-000
1/06