SST89E54RD2A_13 Datasheet, PDF (64/91 Pages) Silicon Storage Technology, Inc – FlashFlex MCU

A Microchip Technology Company
FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
Not Recommended for New Designs
Security Lock Status
The three bits that indicate the device security lock status are located in SFST[7:5]. As shown in Figure
30 and Table 24, the three security lock bits control the lock status of the primary and secondary blocks
of memory. There are four distinct levels of security lock status. In the first level, none of the security
lock bits are programmed and both blocks are unlocked. In the second level, although both blocks are
now locked and cannot be programmed, they are available for read operation via Byte-Verify. In the
third level, three different options are available: Block 1 hard lock / Block 0 SoftLock, SoftLock on both
blocks, and hard lock on both blocks. Locking both blocks is the same as Level 2, Block 1 except read
operation isn’t available. The fourth level of security is the most secure level. It doesn’t allow read/pro-
gram of internal memory or boot from external memory. For details on how to program the security lock
bits refer to the external host mode and in-application programming sections.
UUU/NN
Level 1
PUU/SS
Level 2
UPU/SS
UPP/LL
PPU/LS
UUP/LS
Level 3
PUP/LL
UPP/LL
PPP/LL
Level 4
1339 F29.0
Note: P = Programmed (Bit logic state = 0), U = Unprogrammed (Bit logic state = 1), N = Not Locked, L = Hard locked,
S = Soft locked
Figure 30:Security Lock Levels
©2011 Silicon Storage Technology, Inc.
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DS25114A
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