SST25VF512 Datasheet, PDF (6/23 Pages) Silicon Storage Technology, Inc – 512 Kbit SPI Serial Flash

Data Sheet
Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write oper-
ation, whether the device is Write enabled, and the state of
the memory Write protection. During an internal Erase or
Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 5 describes the function of each bit in the software
status register.
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A “1” for the Busy bit indi-
cates the device is busy with an operation in progress. A “0”
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the inter-
nal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to “1”, it indicates the device is Write enabled. If the
bit is set to “0” (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automati-
cally reset under the following conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming
reached its highest memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
512 Kbit SPI Serial Flash
SST25VF512
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table 4, to be software pro-
tected against any memory Write (Program or Erase)
operations. The Write-Status-Register (WRSR) instruction
is used to program the BP1 and BP0 bits as long as WP#
is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase
can only be executed if Block-Protection bits are both 0.
After power-up, BP1 and BP0 are set to 1.
Block Protection Lock-Down (BPL)
WP# pin driven low (V_IL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the
WP# pin is driven high (V_IH), the BPL bit has no effect and
its value is “Don’t Care”. After power-up, the BPL bit is
reset to 0.
TABLE 4: SOFTWARE STATUS REGISTER
BLOCK PROTECTION¹
Protection Level
Status
Register Bit
BP1 BP0
Protected
Memory Area
0
0
0
None
1
0
(1/4 Memory Array)²
1 0C000H-0FFFFH
2
1
(1/2 Memory Array)
0 08000H-0FFFFH
3
1
(Full Memory Array)
1 00000H-0FFFFH
T4.5 1192
1. Default at power-up for BP1 and BP0 is ‘11’.
2. Protection Level 1 (1/4 Memory Array) applies to Byte-
Program, Sector-Erase, and Chip-Erase operations.
It does not apply to Block-Erase operations.
TABLE 5: SOFTWARE STATUS REGISTER
Bit Name Function
0 BUSY 1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 WEL 1 = Device is memory Write enabled
0 = Device is not memory Write enabled
2 BP0 Indicate current level of block write protection (See Table 4)
3 BP1 Indicate current level of block write protection (See Table 4)
4:5 RES Reserved for future use
6 AAI Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
7 BPL 1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
©2005 Silicon Storage Technology, Inc.
6
Default at Power-up
0
0
1
1
0
0
Read/Write
R
R
R/W
R/W
N/A
R
0
R/W
T5.0 1192
S71192-08-000
11/05