SST39VF088_07 Datasheet, PDF (3/22 Pages) Silicon Storage Technology, Inc – 8 Mbit (x8) Multi-Purpose Flash

8 Mbit Multi-Purpose Flash
SST39VF088
Data# Polling (DQ₇)
When the SST39VF088 is in the internal Program opera-
tion, any attempt to read DQ₇ will produce the complement
of the true data. Once the Program operation is completed,
DQ₇ will produce true data. Note that even though DQ₇
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 µs. During internal Erase operation, any
attempt to read DQ₇ will produce a ‘0’. Once the internal
Erase operation is completed, DQ₇ will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block- or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling
timing diagram and Figure 14 for a flowchart.
Toggle Bit (DQ₆)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ₆ will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ₆ bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block-, or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 6 for Toggle
Bit timing diagram and Figure 14 for a flowchart.
EOL Data Sheet
Data Protection
The SST39VF088 provides both hardware and software
features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V_DD Power Up/Down Detection: The Write operation is
inhibited when V_DD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF088 provides the JEDEC approved Software
Data Protection scheme for all data alteration operations,
i.e., Program and Erase. Any Program operation requires
the inclusion of the three-byte sequence. The three-byte
load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write opera-
tions, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte
sequence. The SST39VF088 device is shipped with the
Software Data Protection permanently enabled. See Table
4 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to Read mode within T_RC.
©2007 Silicon Storage Technology, Inc.
3
S71227-05-EOL
2/07