SST25VF040_10 Datasheet, PDF (3/23 Pages) Silicon Storage Technology, Inc – 4 Mbit SPI Serial Flash

4 Mbit SPI Serial Flash
SST25VF040
PIN DESCRIPTION
EOL Product Data Sheet
CE#
SO
WP#
VSS
1
8
2
7
Top View
3
6
4
5
1231 08-soic P1.0
VDD
HOLD#
SCK
SI
8-LEAD SOIC
CE# 1
SO 2
WP# 3
VSS 4
Top View
8 VDD
7 HOLD#
6 SCK
5 SI
1231 08-wson P2.0
8-CONTACT WSON
FIGURE 2: Pin Assignments
TABLE 1: Pin Description
Symbol
SCK
SI
SO
CE#
WP#
HOLD#
V_DD
V_SS
Pin Name
Serial Clock
Serial Data
Input
Serial Data
Output
Chip Enable
Write Protect
Hold
Power Supply
Ground
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the device.
To provide power supply (2.7-3.6V).
T1.0 1231(04)
©2006 Silicon Storage Technology, Inc.
3
S71231(04)-01-EOL 09/10