SST49LF002A Datasheet, PDF (24/36 Pages) Silicon Storage Technology, Inc – 2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub
SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A
Advance Information
AC CHARACTERISTICS (PP MODE)
TABLE 20: READ CYCLE TIMING PARAMETERS V_DD =3.0-3.6V (PP MODE)
Symbol Parameter
Min
T_RC
Read Cycle Time
270
T_RST
RST# High to Row Address Setup
1
T_AS
R/C# Address Set-up Time
45
T_AH
R/C# Address Hold Time
45
T_AA
Address Access Time
T_OE
Output Enable Access Time
T_OLZ
OE# Low to Active Output
0
T_OHZ
OE# High to High-Z Output
T_OH
Output Hold from Address Change
0
Max
120
60
35
Units
ns
µs
ns
ns
ns
ns
ns
ns
ns
T20.2 504
TABLE 21: PROGRAM/ERASE CYCLE TIMING PARAMETERS V_DD =3.0-3.6V (PP MODE)
Symbol Parameter
Min
Max
T_RST
T_AS
T_AH
T_CWH
T_OES
T_OEH
T_OEP
T_OET
T_WP
T_WPH
T_DS
T_DH
T_IDA
T_BP
T_SE
T_BE
T_SCE
RST# High to Row Address Setup
R/C# Address Setup Time
R/C# Address Hold Time
R/C# to Write Enable High Time
OE# High Setup Time
OE# High Hold Time
OE# to Data# Polling Delay
OE# to Toggle Bit Delay
WE# Pulse Width
WE# Pulse Width High
Data Setup Time
Data Hold Time
Software ID Access and Exit Time
Byte Programming Time
Sector-Erase Time
Block-Erase Time
Chip-Erase Time
1
50
50
50
20
20
40
40
100
100
50
5
150
20
25
25
100
Units
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ms
T21.2 504
TABLE 22: RESET TIMING PARAMETERS, V_DD =3.0-3.6V (PP MODE)
Symbol Parameter
Min
Max
T_PRST
V_DD stable to Reset Low
1
T_RSTP
RST# Pulse Width
100
T_RSTF
RST# Low to Output Float
48
T_RST1
RST# High to Row Address Setup
1
T_RSTE
RST# Low to reset during Sector-/Block-Erase or Program
10
T_RSTC
RST# Low to reset during Chip-Erase
50
1. There will be a reset latency of T_RSTE or T_RSTC if a reset procedure is performed during a Program or Erase operation.
Units
ms
ns
ns
µs
µs
µs
T22.1 504
©2001 Silicon Storage Technology, Inc.
24
S71161-06-000 9/01 504