SST36VF1601 Datasheet, PDF (2/26 Pages) Silicon Storage Technology, Inc – 16 Mbit Concurrent SuperFlash

The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST36VF1601 is offered in 48-lead TSOP and 48-ball
TFBGA packages. See Figures 2 and 3 for pinouts.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Concurrent Read/Write Operation
Dual bank architecture of SST36VF1601 device allows the
Concurrent Read/Write operation whereby the user can
read from one bank while program or erase in the other
bank. This operation can be used when the user needs to
read system code in one bank while updating data in the
other bank.
CONCURRENT READ/WRITE STATE
Bank 1
Read
Read
Write
Write
No Operation
No Operation
Bank 2
No Operation
Write
Read
No Operation
Read
Write
Note: For the purposes of this table, write means to perform Block-,
Sector-, or Chip-Erase or Word-Program operations as appli-
cable to the appropriate bank.
Read Operation
The Read operation of the SST36VF1601 is controlled
by CE# and OE#, both have to be low for the system to
obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the out-
put control and is used to gate data on the output pins.
16 Mbit Concurrent SuperFlash
SST36VF1601
Data Sheet
The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 4).
Word-Program Operation
The SST36VF1601 is programmed on a word-by-word
basis. Before programming, one must ensure that the sec-
tor, in which the word which is being programmed exists, is
fully erased. The Program operation consists of three
steps. The first step is the three-byte load sequence for
Software Data Protection. The second step is to load word
address and word data. During the Word-Program opera-
tion, the addresses are latched on the falling edge of either
CE# or WE#, whichever occurs last. The data is latched on
the rising edge of either CE# or WE#, whichever occurs
first. The third step is the internal Program operation which
is initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initi-
ated, will be completed typically within 10 µs. See Figures 5
and 6 for WE# and CE# controlled Program operation tim-
ing diagrams and Figure 19 for flowcharts. During the Pro-
gram operation, the only valid reads are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Sector- (Block-) Erase Operation
The Sector- (Block-) Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST36VF1601 offers both Sector-Erase and
Block-Erase mode. The sector architecture is based on
uniform sector size of 1 KWord. The Block-Erase mode is
based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. See Figures 10
and 11 for timing waveforms. Any commands issued during
the Sector- or Block-Erase operation are ignored.
Chip-Erase Operation
The SST36VF1601 provides a Chip-Erase operation,
which allows the user to erase all unprotected sectors/
blocks to the “1” state. This is useful when the device must
be quickly erased.
©2001 Silicon Storage Technology, Inc.
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