SST31LF041_03 Datasheet, PDF (2/26 Pages) Silicon Storage Technology, Inc – 4 Mbit Flash + 1 Mbit SRAM ComboMemory

4 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF041 / SST31LF041A
Preliminary Specifications
SST31LF041/041A inherently use less energy during
Erase and Program than alternative flash technologies.
When programming a flash device, the total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter Erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative
flash technologies. The monolithic ComboMemory elimi-
nates redundant functions when using two separate mem-
ories of similar architecture; therefore, reducing the total
power consumption.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
SRAM Operation
With BES# low and BEF# high, the SST31LF041/041A
operate as a 128K x8 CMOS SRAM with fully static opera-
tion requiring no external clocks or timing strobes. The
SRAM is mapped into the first 128 KByte address space of
the device for 041/041A. Read and Write cycle times are
equal.
SRAM Read
The SRAM Read operation of the SST31LF041/041A are
controlled by OE# and BES#, both have to be low with
WE# high, for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. When BES# and
BEF# are high, both memory banks are deselected. OE#
is the output control and is used to gate data from the out-
put pins. The data bus is in high impedance state when
OE# is high. See Figure 3 for the Read cycle timing dia-
gram.
The SST31LF041/041A devices also improve flexibility by
using a single package and a common set of signals to
perform functions previously requiring two separate
devices. To meet high density, surface mount requirements,
the SST31LF041 device is offered in 40-lead TSOP pack-
age and the SST31LF041A device is offered in 32-lead
TSOP package. See Figures 1 and 2 for the pinouts.
Device Operation
The ComboMemory uses BES# and BEF# to control oper-
ation of either the SRAM or the flash memory bank. Bus
contention is eliminated as the monolithic device will not
recognize both bank enables as being simultaneously
active. If both bank enables are asserted (i.e., BEF# and
BES# are both low), the BEF# will dominate while the
BES# is ignored and the appropriate operation will be exe-
cuted in the flash memory bank. SST does not recommend
that both bank enables be simultaneously asserted. All
other address, data, and control lines are shared which
minimizes power consumption and area. The device goes
into standby when both bank enables are raised to V_IHC.
See Table 3 for SRAM operation mode selection.
SRAM Write
The SRAM Write operation of the SST31LF041/041A is
controlled by WE# and BES#; both have to be low for the
system to write to the SRAM. BES# is used for SRAM
bank selection. During the Byte-Write operation, the
addresses and data are referenced to the rising edge of
either BES# or WE#, whichever occurs first. The Write time
is measured from the last falling edge to the first rising edge
of BES# and WE#. OE# can be V_IL or V_IH, but no other
value, for SRAM Write operations. See Figure 4 for the
SRAM Write cycle timing diagram.
Flash Operation
With BEF# active, the SST31LF041/041A operate as a
512K x8 flash memory. The flash memory bank is read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with the
JEDEC standard SDP command sequences. Address and
data are latched during the SDP commands and internally
timed Erase and Program operations. See Table 3 for flash
operation mode selection.
For SST31LF041A only: BES# and OE# share pin 32.
During SRAM operation, pin 32 will function as BES#. Dur-
ing flash operation, pin 32 will function as OE#. When pin 32
(OE#/BES#) is high, the data bus is in high impedance state.
©2003 Silicon Storage Technology, Inc.
2
S71107-05-000
12/03