SST49LF020 Datasheet, PDF (18/38 Pages) Silicon Storage Technology, Inc – 2 Megabit LPC Flash

2 Megabit LPC Flash
SST49LF020
Advance Information
LCLK
RST#
CE#
LFRAME#
LAD[3:0]
LCLK
RST# = VIH
CE# = VIL
LFRAME#
LAD[3:0]
LCLK
RST# = VIH
CE# = VIL
LFRAME#
LAD[3:0]
Memory
Write
1st Start Cycle
0000b 011Xb
1 Clock 1 Clock
xxxxb
Address
xxxxb xxxxb A[19:16] A[15:12] A[11:8]
Load Address "An" in 8 Clocks
A[7:4]
Data
TAR
Sync
A3:0] D3:0] D[7:4] 1111b Tri-State 0000b
Load Data "Dn" in 2 Clocks 2 Clocks
1 Clock
Write the last command (Program or Erase) to the device in LPC mode.
Start next
Command
TAR
0000b
1 Clock
Memory
Read
Start Cycle
Address
TAR
Sync
Data
0000b 010Xb xxxxb xxxxb xxxxb A[19:16] A[15:12] A[11:8] A[7:4] A3:0] 1111b Tri-State 0000b XXXXb X,D6#,XXb
TAR
1 Clock 1 Clock
Load Address in 8 Clocks
2 Clocks 1 Clock
Read the DQ6 to see if internal write complete or not.
Next start
0000b
1 Clock
Memory
Read
Start Cycle
0000b 010Xb
1 Clock 1 Clock
xxxxb
Address
TAR
Sync
Data
xxxxb xxxxb A[19:16] A[15:12] A[11:8] A[7:4] A3:0] 1111b Tri-State 0000b XXXXb X,D6,XXb
Load Address in 8 Clocks
2 Clocks
When internal write complete, the DQ6 will stop toggle.
1 Clock Data out 2 Clocks
Next start
TAR
0000b
1 Clock
526 ILL F20.2
FIGURE 10: TOGGLE BIT TIMING DIAGRAM (LPC MODE)
©2001 Silicon Storage Technology, Inc.
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