SST39WF1601 Datasheet, PDF (16/29 Pages) Silicon Storage Technology, Inc – 16 Mbit (x16) Multi-Purpose Flash Plus

Preliminary Specifications
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
ADDRESS A19-0
CE#
OE#
WE#
DQ₆ and DQ₂
T_CE
T_OEH
T_OE
T_OES
TWO READ CYCLES
WITH SAME OUTPUTS
1297 F07.1
FIGURE 8: Toggle Bits Timing Diagram
ADDRESS A_19-0
SIX-BYTE CODE FOR CHIP-ERASE
5555 2AAA
5555
5555
2AAA
5555
T_SCE
CE#
OE#
WE#
TWP
DQ_15-0
XXAA XX55
XX80
XXAA
XX55
XX10
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15.)
WP# must be held in proper logic state (V_IH) 1 µs prior to and 1µs after the command sequence.
X can be V_IL or V_IH, but no other value.
FIGURE 9: WE# Controlled Chip-Erase Timing Diagram
1297 F08.1
©2006 Silicon Storage Technology, Inc.
16
S71297-01-000
7/06