SST65P542R Datasheet, PDF (15/40 Pages) Silicon Storage Technology, Inc – Remote Controller MCU

Remote Controller MCU
SST65P542R
Advance Information
COP Watchdog Timer Control Register (CWTC)
Location
7
6
5
4
3
2
1
0
Reset Value
000DH
-
-
-
-
-
-
-
CWT_EN
01H
Symbol
CWT_EN
Function
COP watchdog timer enable bit.
0: COP watchdog timer is enabled.
1: COP watchdog timer is disabled.
COP Watchdog Timer Reset Register (CWTR)
Location
7
6
5
4
3
2
1
0
Reset Value
3FF0H
-
-
-
-
-
-
-
CWT_CLR
01H
Symbol
CWT_CLR
Function
This bit is for writing only. For detail explanation of COP Watchdog Timer Reset, please refer to
Section 6.4
0: Write zero to this bit will clear COP watchdog timer.
1: Write one to this bit has no effect. Read this bit will always returns one.
Carrier Generator High Data Register1 (CHR1)
Location
7
6
5
4
3
2
1
0
Reset Value
0010H IROLN CMTPOL PH5
PH4
PH3
PH2
PH1
PH0
00UUUUUUb
Symbol
Function
IROLN
IRO latch control bit. Reading IROLN bit reads the state of the IRO latch. Writing IROLN updates
the IRO latch with the data being written on the negative edge of the internal processor clock
(F_OSC/2). The IRO latch is clear out of reset. Writing to CHR1 to update IROLN will also update
the primary carrier high data value. In addition, writing to CHR1 to update IROLN will update the
CMT polarity bit. Bit 6 should contain the data of CMTPOL polarity bit.
CMTPOL CMT output polarity bit. This bit controls the polarity of the CMT output (IRO).
0: the CMT output is active high.
1: the CMT output is active low.
PH[5:0]
Primary carrier high time data values. When selected, these bits contain the number of input
clocks required to generate the carrier high time periods. When operating in timer mode, CHR1
and CLR1 are always selected. When operating in FSK mode, CHR1, CLR1 and CHR2, CLR2
are alternately selected under control of the modulator. The primary carrier high and low time
values are undefined on the reset. These bits must be written to non-zero values that before the
carrier generator is enabled to avoid spurious results.
Bit 0 to Bit 7 of CHR1 can be used for both reading and writing.
Note:“U” indicates that the bit is unaffected after reset.
©2001 Silicon Storage Technology, Inc.
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