SST49LF004C Datasheet, PDF (15/36 Pages) Silicon Storage Technology, Inc – 4 Mbit / 8 Mbit LPC Serial Flash

4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C / SST49LF008C
Abort Mechanism
If LFRAME# is driven low for one or more clock cycles after
the start of a bus cycle, the cycle will be terminated. The
host may drive the LAD[3:0] with ‘1111b’ (ABORT nibble) to
return the interface to ready mode. The ABORT only
affects the current bus cycle. For a multi-cycle command
sequence, such as the Erase or Program commands,
ABORT doesn’t interrupt the entire command sequence,
only the current bus cycle of the command sequence. The
host can re-send the bus cycle for the aborted command
and continue the command sequence after the device is
ready again.
Response to Invalid Fields for
Firmware Memory Cycle
During an on-going Firmware Memory bus cycle, the
SST49LF00xC will not explicitly indicate that it has received
invalid field sequences. The response to specific invalid
fields or sequences is described as follows:
ID mismatch: If the IDSEL field does not match ID[3:0],
the device will ignore the cycle. See “Multiple Device Selec-
tion for Firmware Memory Cycle” on page 16 for details.
Address out of range: The address sequence is 7
fields long (28 bits) with Firmware Memory bus cycles.
Only some of the address fields bits are decoded by the
SST49LF00xC devices. SST49LF004c decodes A₀
through A₁₈ and A_22, and SST49LF008C decodes A₀
through A₁₉ and A₂₂. Address A₂₂ has the special function
of directing reads and writes to the flash core (A₂₂=1) or to
the register space (A₂₂=0).
Advance Information
Invalid MSIZE field: If the SST49LF00xC receives an
invalid size field during a Firmware Memory Read or Write
operation, the device will reset and no operation will be
attempted. The device will not generate any kind of
response in this situation. The SST49LF00xC will only
respond to values listed in Table 6.
TABLE 6: VALID MSIZE FIELD VALUES FOR
FIRMWARE MEMORY CYCLES
MSIZE
0000
0001
0010
0100
0111
Direction
R/W
R/W
R/W
R
R
Size of Transfer
1 Byte
2 Byte
4 Byte
16 Byte
128 Byte
T6.0 1292
Once valid START, IDSEL, and MSIZE are received, the
SST49LF00xC will always complete the bus cycle. How-
ever, if the device is busy performing a flash Erase or Pro-
gram operation, no new internal memory Write will be
executed. As long as the states of LAD[3:0] and LFRAME#
are known, the response of the ST49LF00xC to signals
received during the cycle is predictable.
Non-boundary-aligned address: The SST49LF00xC
accepts multi-byte transfers for both Read and Write opera-
tions. The device address space is divided into uniform
page sizes 2, 4, 16, or 128 bytes wide, according to the
MSIZE value (see Table 6). The host issues only one
address in the MADDR field of the Firmware Memory
Cycle, but multiple bytes are read from or written to the
device. For this reason the MADDR address should be
page boundary-aligned. This means the address should be
aligned to a Word boundary (A₀ = 0) for a 2-byte transfer, a
double Word boundary (e.g. A₀ = 0, A₁ = 0) for a 4-byte
transfer, and so on. If the address supplied by the host is
not page boundary-aligned, the SST49LF00xC will force a
boundary alignment, starting the multi-byte Read or Write
operation from the lower byte of the addressed page.
©200 Silicon Storage Technology, Inc.
15
S71292-00-000
1/06