SST25VF080B Datasheet, PDF (15/28 Pages) Silicon Storage Technology, Inc – 8 Mbit SPI Serial Flash

8 Mbit SPI Serial Flash
SST25VF080B
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the
selected 32 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. The
64-KByte Block-Erase instruction clears all bits in the
selected 64 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. Prior to
any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the
duration of any command sequence. The 32-Kbyte Block-
Erase instruction is initiated by executing an 8-bit com-
mand, 52H, followed by address bits [A₂₃-A₀]. Address bits
[A_MS-A₁₅] (A_MS = Most Significant Address) are used to
Data Sheet
determine block address (BA_X), remaining address bits can
be V_IL or V_IH. CE# must be driven high before the instruction
is executed. The 64-Kbyte Block-Erase instruction is initi-
ated by executing an 8-bit command D8H, followed by
address bits [A₂₃-A₀]. Address bits [A_MS-A₁₅] are used to
determine block address (BA_X), remaining address bits can
be V_IL or V_IH. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait T_BE for the completion of the internal
self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 12 and 13 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
CE#
MODE 3
SCK ^{MODE 0}
0 1 2345 6 78
15 16
23 24 31
SI
52
ADDR ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
1296 32KBklEr.0
FIGURE 12: 32-KBYTE BLOCK-ERASE SEQUENCE
CE#
MODE 3
SCK ^{MODE 0}
0 1 2345 6 78
15 16
23 24 31
SI
D8
ADDR ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
1296 63KBlkEr.0
FIGURE 13: 64-KBYTE BLOCK-ERASE SEQUENCE
©2006 Silicon Storage Technology, Inc.
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