SST26WF032 Datasheet, PDF (12/36 Pages) Silicon Storage Technology, Inc – 1.8V Serial Quad I/O (SQI) Flash Memory

1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Table 3: Device Operation Instructions for SST26WF032
Instruction
Description
Command _{Address Dummy}
Data
Maximum
Cycle¹
Cycle(s)² Cycle(s) Cycle(s) Frequency
WRDI
Write Disable
04H
0
0
0
RBPR¹²
Read Block Protec-
72H
0
0
1 to m/4
tion Register
WBPR^10,12
Write Block Protec-
42H
0
0
1 to m/4
80 MHz
tion Register
LBPR¹⁰
Lock Down Block
8DH
0
0
0
Protection Register
1. One BUS cycle is two clock periods (command, access, or data).
T3.0 1409
2. Address bits above the most significant bit of each density can be V_IL or V_IH.
3. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
4. Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
5. After a power cycle, Read, High-Speed Read, and JEDEC-ID Read instructions input and output cycles are SPI bus
protocol.
6. Burst length– n = 8 Bytes: Data(00H); n = 16 Bytes: Data(01H); n = 32 Bytes: Data(02H); n = 64 Bytes: Data(03H).
7. The Quad J-ID read wraps the three Quad J-ID Bytes of data until terminated by a low-to-high transition on CE#
8. Sector Addresses: Use A_MS - A₁₂, remaining address are don’t care, but must be set to V_IL or V_IH.
9. Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: A_MS - A₁₆ for 64 KByte; A_MS -
A₁₅ for 32 KByte; A_MS - A₁₃ for 8 KByte. Remaining addresses are don’t care, but must be set to V_IL or V_IH.
10. Requires a prior WREN command.
11. The Read-Status register is continuous with ongoing clock cycles until terminated by a low-to-high transition on CE#.
12. Data is written/read from MSB to LSB. MSB = 79 for SST26WF032.
No Operation (NOP)
The No Operation command only cancels a Reset Enable command. NOP has no impact on any other
command.
©2010 Silicon Storage Technology, Inc.
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