SST34HF1642D Datasheet, PDF (11/38 Pages) Silicon Storage Technology, Inc – 16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory

16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1602C / SST34HF1622C / SST34HF1642C
SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S
Advance Information
TABLE 3: PIN DESCRIPTION
Symbol Pin Name
Functions
A_MS1 to A₀ Address Inputs
To provide flash address, A₁₉-A₀.
To provide (P)SRAM address, A_MS-A₀
SA
SRAM x8 Address
To provide additional address for x8 SRAM
DQ₁₄-DQ₀ Data Inputs/Outputs
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle. The outputs are in
tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.
DQ₁₅/A_-1 Data Input/Output
and LBS Address
DQ₁₅ is used as data I/O pin when in x16 mode (CIOF = “1”)
A_-1 is used as the LBS address pin when in x8 mode (CIOF = “0”)
BEF#
Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low
BES1# (P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES1# is low
BES2
(P)SRAM Memory Bank Enable To activate the (P)SRAM memory bank when BES2 is high
OEF#² Output Enable
To gate the data output buffers for Flash² only
OES#² Output Enable
To gate the data output buffers for SRAM² only
WEF#² Write Enable
To control the Write operations for Flash² only
WES#² Write Enable
To control the Write operations for SRAM² only
OE#
Output Enable
To gate the data output buffers
WE#
Write Enable
To control the Write operations
CIOF
Byte Selection for Flash
When low, select Byte mode. When high, select Word mode.
UBS#
LBS#
Upper Byte Control ((P)SRAM) To enable DQ₁₅-DQ₈
Lower Byte Control ((P)SRAM) To enable DQ₇-DQ₀
WP#
Write Protect
To protect and unprotect the top 8 KWord (4 sectors) from Erase or Program
operation
RST#
Reset
To Reset and return the device to Read mode
RY/BY# Ready/Busy#
To output the status of a Program or Erase Operation
RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to
allow RY/BY# to transition high indicating the device is ready to read.
V_SSF2
V_SSS2
V_SS
V_DDF
V_DDS
NC
Ground
Ground
Ground
Power Supply (Flash)
Power Supply ((P)SRAM)
No Connection
Flash² only
SRAM² only
2.7-3.3V Power Supply to Flash only
2.7-3.3V Power Supply to (P)SRAM only
Unconnected pins
1. A_MS = Most Significant Address
A_MS = A₁₆ for SST34HF1622C/S, A₁₇ for SST34HF1642C/D/S, and A₁₈ for SST34HF1682D
2. LS package only
T3.0 1256
©2004 Silicon Storage Technology, Inc.
11
S71256-00-000
3/04