SST45VF512 Datasheet, PDF (1/16 Pages) Silicon Storage Technology, Inc – 512 Kbit / 1 Mbit / 2 Mbit Serial Flash

512 Kbit / 1 Mbit / 2 Mbit Serial Flash
SST45VF512 / SST45VF010 / SST45VF020
Advance Information
FEATURES:
• Single 2.7-3.6V Read and Write Operations
• Automatic Write Timing
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• Serial Interface Architecture
– Internal VPP Generation
– SPI Compatible: Mode 0 and Mode 3
• Byte Serial Read with Single Command
• End-of-Write Detection
– Software Status
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• 10 MHz Max Clock Frequency
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
• Hardware Reset Pin (RESET#)
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– Greater than 100 years Data Retention
– Resets the device to Standby Mode
• Low Power Consumption:
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
• Sector or Chip-Erase Capability
– Uniform 4 KByte sectors
• CMOS I/O Compatibility
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• Hardware Data Protection
– Protects and unprotects the device
from Write operation
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• Packages Available
• Fast Erase and Byte-Program:
– 8-Pin SOIC (4.9mm x 6mm)
– Chip-Erase Time: 70 ms (typical)
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– Sector-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µs (typical)
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PRODUCT DESCRIPTION
Read
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The SST45VF512, SST45VF010 and SST45VF020 are ^{The Read operation outputs the data in order from the}
manufactured with SST’s proprietary, high performance
CMOS SuperFlash technology. The Serial Flash is
initial accessed address. While SCK is input, the address
will be incremented automatically until end (top) of the
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organized as 16 sectors of 4096 Bytes for SST45VF512, ^{address space, then the internal address pointer auto-}
32 sectors of 4096 Bytes for the SST45VF010 and
64 sectors of 4096 Bytes for the SST45VF020. The
matically increments to beginning (bottom) of the ad-
dress space (00000H), and data out stream will continue.
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memory is accessed for Read or Erase/Program by the ^{The read data stream is continuous through all ad-}
SPI bus compatible serial protocol. The bus signals are: ^{dresses until terminated by a low to high transition on}
serial data input (SI), serial data output (SO), serial clock ^CE#.
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(SCK), write protect (WP#), chip enable (CE#), and
hardware reset (RESET#).
Sector/Chip-Erase Operation
The SST45VFxxx devices are offered in 8-pin SOIC
The Sector-Erase operation clears all bits in the selected
sector to “FF”. The Chip-Erase instruction clears all bits
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package. See Figure 1 for the pinout.
in the device to “FF”.
Device Operation
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Byte-Program Operation
The SST45VFxxx uses bus cycles of 8 bits each for
The Byte-Program operation programs the bits in the
commands, data, and addresses to execute operations.
The operation instructions are listed in Table 2.
selected byte to the desired data. The selected byte must
be in the erased state (“FF”) when initiating a Program
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All instructions are synchronized off a high to low transi- ^{operation. The data is input from bit 7 to bit 0 in order.}
tion of CE#. The first low to high transition on SCK will
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initiate the instruction sequence. Inputs will be accepted ^{Software Status Operation}
on the rising edge of SCK starting with the most signifi- ^{The Status operation determines if an Erase or Program}
cant bit. Any low to high transition on CE# before the input
operation is in progress. If bit 0 is at a “0” an Erase or
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instruction completes will terminate any instruction in ^{Program operation is in progress, the device is busy. If bit}
progress and return the device to the standby mode.
0 is at a “1” the device is ready for any valid operation. The
status read is continuous with ongoing clock cycles until
terminated by a low to high transition on CE#.
© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
514-1 10/00
S71178
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