SST39VF160Q Datasheet, PDF (1/23 Pages) Silicon Storage Technology, Inc – 16 Megabit (1M x 16-Bit) Multi-Purpose Flash

16 Megabit (1M x 16-Bit) Multi-Purpose Flash
SST39VF160Q / SST39VF160
Advance Information
FEATURES:
• Organized as 1 M X 16
• Latched Address and Data
• Single 2.7V-only Read and Write Operations
• Fast Sector Erase and Word Program:
1
• VDDQ Power Supply to Support 5V I/O
- Sector Erase Time: 3 ms typical
for SST39VF160Q
- VDDQ not available on SST39VF160
- Block Erase Time: 7 ms typical
- Chip Erase Time: 15 ms typical
- Word Program time: 7 µs typical
2
• Superior Reliability
- Chip Rewrite Time: 7 seconds
- Endurance: 100,000 Cycles (typical)
• Automatic Write Timing
3
- Greater than 100 years Data Retention
- Internal Vpp Generation
• Low Power Consumption:
- Active Current: 15 mA (typical)
- Standby Current: 3 µA (typical)
- Auto Low Power Mode: 3 µA (typical)
• End of Write Detection
- Toggle Bit
- Data# Polling
4
• Small Sector Erase Capability (512 sectors)
• CMOS I/O Compatibility
5
- Uniform 2 KWord sectors
• JEDEC Standard
• Block Erase Capability (32 blocks)
- Uniform 32 KWord blocks
- EEPROM Pinouts and command set
• Packages Available
6
• Fast Read Access Time:
- 70 and 90 ns
- 48-Pin TSOP (12mm x 20mm)
- 6 x 8 Ball TFBGA
7
PRODUCT DESCRIPTION
alternative flash technologies. The total energy con-
The SST39VF160Q/VF160 devices are 1M x 16 CMOS
Multi-Purpose Flash (MPF) manufactured with SST’s
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
8
proprietary, high performance CMOS SuperFlash tech-
SuperFlash technology uses less current to program and
nology. The split-gate cell design and thick oxide tunnel-
ing injector attain better reliability and manufacturability
has a shorter erase time, the total energy consumed
during any Erase or Program operation is less than
9
compared with alternate approaches. The
alternative flash technologies. The SST39VF160Q/
SST39VF160Q/VF160 write (Program or Erase) with a
2.7V-only power supply. The SST39VF160Q/VF160
VF160 also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
10
conform to JEDEC standard pinouts for x16 memories. _{The SuperFlash technology provides fixed Erase and}
Featuring high performance word program, the
Program times, independent of the number of endurance
11
SST39VF160Q/VF160 devices provide a maximum
cycles that have occurred. Therefore the system
word-program time of 10 µsec. The entire memory can
software or hardware does not have to be modified or
typically be erased and programmed word by word in 7
seconds, when using interface features such as Toggle
de-rated as is necessary with alternative flash technolo-
gies, whose erase and program times increase with
12
Bit or Data# Polling to indicate the completion of Program
accumulated endurance cycles.
operation. To protect against inadvertent write, the
To meet high density, surface mount requirements, the
13
SST39VF160Q/VF160 have on-chip hardware and soft- _{SST39VF160Q/VF160 are offered in 48-pin TSOP and}
ware data protection schemes. Designed, manufac- _{48-pin TFBGA packages. See Figures 1 and 2 for}
tured, and tested for a wide spectrum of applications, the _pinouts.
14
SST39VF160Q/VF160 are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at _{Device Operation}
greater than 100 years.
Commands are used to initiate the memory operation ₁₅
The SST39VF160Q/VF160 devices are suited for appli-
functions of the device. Commands are written to the
cations that require convenient and economical updating
device using standard microprocessor write sequences.
of program, configuration, or data memory. For all sys-
A command is written by asserting WE# low while
16
tem applications, the SST39VF160Q/VF160 signifi-
keeping CE# low. The address bus is latched on the
cantly improve performance and reliability, while lower-
falling edge of WE# or CE#, whichever occurs last. The
ing power consumption. The SST39VF160Q/VF160 in-
data bus is latched on the rising edge of WE# or CE#,
herently use less energy during Ease and Program than
whichever occurs first.
© 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc.
329-09 11/98
1
These specifications are subject to change without notice.