SST32HF64A2 Datasheet, PDF (1/38 Pages) Silicon Storage Technology, Inc – Multi-Purpose Flash Plus + PSRAM ComboMemory

Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF64A2
FEATURES:
SST32HF64A1 / 64B164Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM
(x16) MCP ComboMemories
Preliminary Specifications
• ComboMemories organized as:
– SST32HF64A2: 4M x16 Flash + 1024K x16 PSRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or Write to PSRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or PSRAM Read
– Standby Current: 60 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Erase-Suspend/Erase-Resume Capabilities
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Fast Read Access Times:
– Flash: 70 ns
– PSRAM: 70 ns
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST32HF64A2
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Flash Automatic Erase and Program Timing
– Internal V_PP Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 56-ball LFBGA (8mm x 10mm x 1.4mm)
– 64-ball LFBGA (8mm x 10mm x 1.4mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HF64A2 ComboMemory device integrates a
CMOS flash memory bank with a CMOS PseudoSRAM
(PSRAM) memory bank in a Multi-Chip Package (MCP),
manufactured with SST proprietary, high-performance
SuperFlash technology.
Featuring high-performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. To protect against inadvertent flash write, the
SST32HF64A2 device contains on-chip hardware and soft-
ware data protection schemes. The SST32HF64A2 device
offers a guaranteed endurance of 10,000 cycles, and data
retention greater than 100 years.
The SST32HF64A2 device consists of two independent
memory banks, each with enable signals. The flash and
PSRAM memory banks are superimposed in the same
memory address space, and both banks share common
address lines, data lines, WE# and OE#. The memory
bank is selected using the memory bank enable signals.
The PSRAM bank enable signal, BES1#, selects the
PSRAM bank. The flash memory bank enable signal,
BEF#, selects the flash memory bank. The WE# signal is
used with the Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST32HF64A2 provides the added functionality of
being able to simultaneously read from, or write to, the
PSRAM bank while erasing or programming in the flash
memory bank. The PSRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
required. Once the internally controlled Erase or Program
cycle in the flash bank commences, the PSRAM bank can
be accessed for Read or Write.
©2006 Silicon Storage Technology, Inc.
S71299-02-000
11/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.