SST29EE010_04 Datasheet, PDF (1/27 Pages) Silicon Storage Technology, Inc – 1 Megabit (128K x 8) Page Mode EEPROM

1 Megabit (128K x 8) Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Data Sheet
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for the 29EE010
– 3.0V-only for the 29LE010
– 2.7V-only for the 29VE010
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-write Cycle Time: 39 µs
(typical)
• Fast Read Access Time
– 5.0V-only operation: 90 and 120 ns
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– 3.0V-only operation: 150 and 200 ns
– 2.7V-only operation: 200 and 250 ns
• Latched Address and Data
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• Automatic Write Timing
– Internal Vpp Generation
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• End of Write Detection
– Toggle Bit
– Data# Polling
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• Hardware and Software Data Protection
• TTL I/O Compatibility
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• JEDEC Standard Byte-wide EEPROM Pinouts
• Packages Available
– 32-Pin TSOP (8x20 & 8x14 mm)
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– 32-Lead PLCC
– 32 Pin Plastic DIP
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PRODUCT DESCRIPTION
applications, the 29EE010/29LE010/29VE010 signifi-
cantly improve performance and reliability, while lower- ₈
The 29EE010/29LE010/29VE010 are 128K x 8 CMOS ^{ing power consumption, when compared with floppy disk}
page mode EEPROMs manufactured with SST’s propri- ^{or EPROM approaches. The 29EE010/29LE010/}
etary, high performance CMOS SuperFlash technology.
29VE010 improve flexibility while lowering the cost for
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The split gate cell design and thick oxide tunneling ^{program, data, and configuration storage applications.}
injector attain better reliability and manufacturability
To meet high density, surface mount requirements, the
compared with alternate approaches. The 29EE010/
29EE010/29LE010/29VE010 are offered in 32-pin
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29LE010/29VE010 write with a single power supply.
TSOP and 32-lead PLCC packages. A 600-mil, 32-pin
Internal Erase/Program is transparent to the user. The
PDIP package is also available. See Figures 1 and 2 for
29EE010/29LE010/29VE010 conform to JEDEC stan-
pinouts.
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dard pinouts for byte-wide memories.
Featuring high performance page write, the 29EE010/ ^{Device Operation}
29LE010/29VE010 provide a typical byte-write time of
The SST page mode EEPROM offers in-circuit electrical
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39 µsec. The entire memory, i.e., 128K bytes, can be ^{write capability. The 29EE010/29LE010/29VE010 does}
written page by page in as little as 5 seconds, when using ^{not require separate erase and program operations. The}
interface features such as Toggle Bit or Data# Polling to
internally timed write cycle executes both erase and
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indicate the completion of a write cycle. To protect ^{program transparently to the user. The 29EE010/}
against inadvertent write, the 29EE010/29LE010/ ^{29LE010/29VE010 have industry standard optional}
29VE010 have on-chip hardware and software data
Software Data Protection, which SST recommends al-
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protection schemes. Designed, manufactured, and ^{ways to be enabled. The 29EE010/29LE010/29VE010}
tested for a wide spectrum of applications, the 29EE010/ ^{are compatible with industry standard EEPROM pinouts}
29LE010/29VE010 are offered with a guaranteed page- ^{and functionality.}
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write endurance of 10⁴ or 10³ cycles. Data retention is
rated at greater than 100 years.
Read
The 29EE010/29LE010/29VE010 are suited for applica-
The Read operations of the 29EE010/29LE010/
29VE010 are controlled by CE# and OE#, both have to
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tions that require convenient and economical updating of
be low for the system to obtain data from the outputs.
program, configuration, or data memory. For all system
CE# is used for device selection. When CE# is high, the
© 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
304-04 12/97
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