SS6550 Datasheet, PDF (8/13 Pages) Silicon Standard Corp. – Low-Noise Synchronous PWM Step-Down DC/DC Converter

n BLOCK DIAGRAM
SS6550
BP
SHDN
RT
SYNC
FB
0.75V
REF
Current AMP.
+
X5
-
500KHz
Oscillator
Frequency
Selection
Slope
Compensation
FB
REF
Phase
Compensation
Error
-
AMP.
+
PWM
Comparator
-
+
Chip Supply ¹⁰
VIN
Current Limit
Comparator
+
-
REF
Control Logic
A n t i-
Shoot-
Through
REF
-
+
PFM
Comparator
PWM/PFM
Control
Zero Cross
Comparator
-
+
VIN
5
Q1
Q1
x1
X20
LX
Q3
GND
n PIN DESCRIPTIONS
PIN 1: VIN- Supply voltage input. Input range
from +2.5V to +5.5V. Bypass with a
10µF capacitor.
PIN 2: BP- Supply bypass pin, internally con-
nected to VIN. Bypass with a 0.1µF
capacitor. Do not connect to an ex-
ternal power source other than VIN.
PIN 3: SHDN - Active-low, shutdown-control input.
Reduces supply current to 0.1µA in
shutdown.
PIN 4: FB- Feedback input.
PIN 5: RT- Frequency adjustable pin. Connect a
resistor from this pin to GND to de-
crease the frequency.
PIN 6: SYNC/MODE- Oscillator sync and low-noise,
mode-control Input.
SYNC/MODE = VIN (Forced PWM
mode)
SYNC/MODE = GND (PWM/PFM
mode)
An external clock signal connected
to this pin allows for LX switching
synchronization.
PIN 7: GND- Ground.
PIN 8: LX-
Inductor connection to the drains of
the internal power MOSFETs
Rev.2.01 6/06/2003
www.SiliconStandard.com
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