W311 Datasheet, PDF (8/18 Pages) Silicon Laboratories – FTG for VIA™ Pro-266 DDR Chipset

W311
Byte 9: System Reset and Watchdog Timer Register
Bit
Name
Default
Pin Description
Bit 7
Bit 6
Reserved
PCI_DRV
0
Reserved
0
PCI clock output drive strength
0 = Normal
1 = High Drive
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reserved
RST_EN_WD
RST_EN_FC
WD_TO_STATU
S
WD_EN
0
Reserved
0
This bit will enable the generation of a Reset pulse when a watchdog timer
time-out occurs.
0 = Disabled
1 = Enabled
0
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
0
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
0
0 = Stop and re-load Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down after a frequency
change occurs.
Note: :ZLOOJHQHUDWHV\VWHPUHVHWUHORDGDUHFRYHU\IUHTXHQF\DQGORFN
itself into a recovery frequency mode after a watchdog timer time-out occurs.
Under recovery frequency mode, W311 will not respond to any attempt to
change output frequency via the SMBus control bytes. System software can
unlock W311 from its recovery frequency mode by clearing the WD_EN bit.
Bit 0
Reserved
0
Reserved
Byte 10: Skew Control Register
Bit
Name
Bit 7
Bit 6
Bit 5
CPU_Skew2
CPU_Skew1
CPU_Skew0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
AGP_Skew1
AGP_Skew0
Default
0
0
0
0
0
0
0
0
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Reserved
Reserved
Reserved
AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Description
Rev 1.0, November 25, 2006
Page 8 of 18