W137 Datasheet, PDF (7/8 Pages) Cypress Semiconductor – Bx Notebook System Frequency Synthesizer

W137
PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
t_P
Period
Measured on rising edge at 1.5V
t_H
High Time
Duration of clock cycle above 2.4V
t_L
Low Time
Duration of clock cycle below 0.4V
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference
of cycle time between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V
t_O
CPU to PCI Clock Offset Covers all CPU/PCI outputs. Measured on rising edge
at 1.5V. CPU leads PCI output.
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold power-up. Short cycles exist prior to frequency stabili-
start)
zation.
Z_o
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
Min.
30
12.0
12.0
1
1
45
1.5
Typ.
20
Max.
4
4
55
250
500
4.0
3
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
:
REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min.
f
Frequency, Actual
Determined by crystal oscillator frequency
14.318
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
f_ST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
Power-up (cold start)
from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Max.
25
Typ.
2
2
55
3
Unit
MHz
V/ns
V/ns
%
ms
:
48 MHz and 24 MHz Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
Test Condition/Comments
Determined by PLL divider ratio (see n/m below)
f_D
Deviation from 48 MHz
(48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
Power-up (cold start)
from power-up. Short cycles exist prior to frequency
stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
48.008
24.004
+167
57/17, 57/34
0.5
2
0.5
2
45
55
3
25
Unit
MHz
ppm
V/ns
V/ns
%
ms
:
Rev 1.0, November 24, 2006
Page 7 of 8