CY28400-2 Datasheet, PDF (6/15 Pages) SpectraLinear Inc – 100 MHz Differential Buffer for PCI Express and SATA

CY28400-2
OE_INV
0
0
1
1
PWRDWN
0
1
0
1
Mode
Power Down
Normal
Normal
Power Down
PWRDWN—Assertion
When the power-down pin is sampled as being asserted by
two consecutive rising edges of DIFC, all DIFT outputs will be
held high or tri-stated (depending on the state of the control
register drive mode and OE bits) on the next DIFC high to low
transition. When the SMBus PWRDWN Drive Mode bit is
programmed to ‘0’, all clock outputs will be held with the DIFT
pin driven high at 2 x Iref and DIFC tri-stated. However, if the
control register PWRDWN Drive Mode bit is programmed to
‘1’, then both DIFT and the DIFC are tri-stated.
PWRDWN—Deassertion
The power-up latency is less than 1 ms. This is the time from
the deassertion of the PWRDWN pin or the ramping of the
power supply or the time from valid SRC_IN input clocks until
the time that stable clocks are output from the buffer chip (PLL
locked). IF the control register PWRDWN Drive Mode bit is
programmed to ‘1’, all differential outputs must be driven high
in less than 300 Ps of the power down pin deassertion to a
voltage greater than 200 mV.
PWRDWN
DIFT
DIFC
Figure 1. PWRDWN Assertion Diagram, OE_INV = 0
PWRDWN
DIFT
DIFC
Figure 2. PWRDWN Assertion Diagram, OE_INV = 1
PWRDWN
DIFT
DIFC
PWRDWN
DIFT
DIFC
Tstable
<1 ms
Tdrive_Pwrdwn#
<300 µs, >200 mV
Figure 3. PWRDWN Deassertion Diagram, OE_INV = 0
Tstable
<1 ms
Tdrive_Pwrdwn#
<300 µs, >200 mV
Figure 4. PWRDWN Deassertion Diagram, OE_INV = 1
Rev 1.0, November 21, 2006
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