W256 Datasheet, PDF (5/7 Pages) Cypress Semiconductor – 12 Output Buffer for 2 DDR and 3 SRAM DIMMS

W256
Switching Characteristics^[4]
Parameter
t_3d
t_4d
t₅
t₆
t₇
t₈
Name
DDR Rising Edge Rate^[4]
DDR Falling Edge Rate^[4]
Output to Output Skew^[4]
Output t4o Output Skew for
SDRAM^[2]
SDRAM Buffer HH Prop. Delay^[4]
SDRAM Buffer LLProp. Delay^[4]
Test Conditions
Measured between 20% to 80% of
output (Refer to Figure 1)
Measured between 20% to 80% of
output (Refer to Figure 1)
All outputs equally loaded
All outputs equally loaded
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Switching Waveforms
Duty Cycle Timing
t₁
t₂
Min.
0.5
0.5
5
5
Typ.
Max.
1.50
1.50
100
150
10
10
Unit
V/ns
V/ns
ps
ps
ns
ns
All Outputs Rise/Fall Time
2.4V
OUTPUT _0.4V
t₃
2.4V
0.4V
t₄
3.3V
0V
Output-Output Skew
OUTPUT
OUTPUT
t₅
SDRAM Buffer HH and LL Propagation Delay
INPUT
1.5V
OUTPUT
1.5V
t₆
t₇
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.
Rev 1.0, November 25, 2006
Page 5 of 7