CY28SRC01 Datasheet, PDF (5/9 Pages) SpectraLinear Inc – PCI-Express Clock Generator

CY28SRC01
Byte 6: Control Register 6
Bit
@Pup
Name
4
1
Reserved
3
0
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2
0
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1
1
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0
1
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Reserved
Reserved
Reserved
Reserved
Description
Byte 7: Control Register 7
Bit
@Pup
7
0
6
0
5
1
4
1
3
1
2
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
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Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Table 4. Crystal Recommendations
Frequency
(Fund)
14.31818 MHz
Cut Loading
AT Parallel
Load Cap
12pF - 16pF
Drive
(max.)
1mW
Shunt Cap
(max.)
7 pF
Tolerance
(max.)
+ 50ppm
Stability
(max.)
+ 50ppm
Aging
(max.)
5 ppm
Crystal Recommendations
The CY28SRC01 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28SRC01 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Clock Chip
Ci1
Ci2
Pin
3 to 6p
X1
Cs1
X2
Cs2
XTAL
Trace
2.8pF
Figure 1. Crystal Capacitive Clarification
Ce1
Ce2
Trim
27pF
Figure 2. Crystal Loading Example
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This means the total capac-
Rev 1.0, November 20, 2006
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