W255 Datasheet, PDF (4/9 Pages) SpectraLinear Inc – 200 MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS

W255
Maximum Ratings
Supply Voltage to Ground Potential..................–0.5 to +7.0V
DC Input Voltage (except BUF_IN)............ –0.5V to V_DD+0.5
Operating Conditions^[2]
Storage Temperature...................................–65°C to +150°C
Static Discharge Voltage .......................................... > 2000V
(per MIL-STD-883, Method 3015)
Parameter
VDD3.3
VDD2.5
T_A
C_OUT
C_IN
Description
Supply Voltage
Supply Voltage
Operating Temperature (Ambient Temperature)
Output Capacitance
Input Capacitance
Min.
Typ.
Max.
Unit
3.135
3.465
V
2.375
2.625
V
0
70
°C
6
pF
5
pF
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
V_IL
Input LOW Voltage
For all pins except SMBus
0.8
V
V_IH
Input HIGH Voltage
2.0
V
I_IL
Input LOW Current
V_IN = 0V
50
PA
I_IH
Input HIGH Current
V_IN = V_DD
50
PA
I_OH
Output HIGH Current
V_DD = 2.375V
–18
–32
mA
V_OUT = 1V
I_OL
Output LOW Current
V_DD = 2.375V
26
35
mA
V_OUT = 1.2V
V_OL
Output LOW Voltage^[3]
I_OL = 12 mA, V_DD = 2.375V
0.6
V
V_OH
Output HIGH Voltage^[3]
I_OH = –12 mA, V_DD = 2.375V
1.7
V
I_DD
Supply Current^[3]
Unloaded outputs, 133 MHz
(DDR-only mode)
400
mA
I_DD
Supply Current
Loaded outputs, 133 MHz
(DDR-only mode)
500
mA
I_DDS
V_OUT
Supply Current
PWR_DWN# = 0
Output Voltage Swing
See test circuity (refer to
0.7
Figure 1)
100
PA
V_DD +0.6
V
V_OC
Output Crossing Voltage
(V_DD/2) – V_DD/2 (V_DD/2) +
V
0.1
0.1
IN_DC
Input Clock Duty Cycle
48
52
%
Switching Characteristics ^[4]
Parameter
Name
Test Conditions
Min. Typ. Max.
–
Operating Frequency
66
–
Duty Cycle^{[3, 5]} = t₂ yt₁
Measured at 1.4V for 3.3V outputs IN_DC –
Measured at V_DD/2 for 2.5V outputs 5%
t₃
SDRAM Rising Edge Rate^[3]
Measured between 0.4V and 2.4V
1.0
t₄
SDRAM Falling Edge Rate^[3]
Measured between 2.4V and 0.4V
1.0
t_3d
DDR Rising Edge Rate^[3]
Measured between 20% to 80% of
0.5
output (refer to Figure 1)
200
IN_DC +
5%
2.75
2.75
1.50
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Unit
MHz
%
V/ns
V/ns
V/ns
Rev 1.0, November 25, 2006
Page 4 of 9