W164 Datasheet, PDF (4/11 Pages) Cypress Semiconductor – Spread Spectrum Desktop/Notebook System Frequency Generator

W164
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
V_DD
W164
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
10 k:
(Load Option 1)
10 k:
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
W164
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
Jumper Options
10 k:
V_DD
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
Serial Data Interface
The W164 features a two-pin, serial data interface that can be
used to configure internal register settings that control
particular device functions. Upon power-up, the W164
initializes with default register settings. Therefore, the use of
this serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. Clock device register changes are
normally made upon system initialization, if required. The
interface can also be used during system operation for power
management functions. Table 2 summarizes the control
functions of the serial data interface.
Operation
Data is written to the W164 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond
the 100- and 66.6-MHz selections that are provided
by the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input,
internal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved)
Reserved function for future device revision or
production device testing.
No user application. Register bit must be
written as 0.
Rev 1.0, November 28, 2006
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