CY28SRC02 Datasheet, PDF (3/9 Pages) SpectraLinear Inc – PCI-Express Clock Generator

CY28SRC02
Table 2. Block Read and Block Write Protocol (continued)
Bit
36:29
Block Write Protocol
Description
Data byte 1 – 8 bits
37
45:38
46
....
....
....
....
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
Bit
28
29
37:30
38
46:39
47
55:48
56
....
....
....
Block Read Protocol
Description
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
Description
1
Start
8:2 Slave address – 7 bits
9
Write
10 Acknowledge from slave
18:11
19
27:20
28
29
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Byte Read Protocol
Description
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Control Registers
Byte 0:Control Register 0
Bit
@Pup
Name
7
0
Reserved
6
1
SRC[T/C]4
5
1
SRC[T/C]3
4
1
SRC[T/C]2
3
1
SRC[T/C]1
2
1
SRC [T/C]0
Description
Reserved
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z),
1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z),
1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z)
1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Rev 1.0, November 20, 2006
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