CY28324 Datasheet, PDF (20/21 Pages) Cypress Semiconductor – FTG for Intel Pentium 4 CPU and Chipsets

Layout Example
CY28324
FB
VDDQ3
0.005PF
C4
C3
GG
G
G
G
VDDQ3
5:
1
48
G
2^V
47
3^G
V ₄₆
G
4
G ₄₅
5^G
44
6
G ₄₃
7
42
8^G
41
9^V
G ₄₀
10 ^G
V ₃₉
G
11
G ₃₈
12
37
13 ^G
G ₃₆
14
35
15
V ₃₄
G
16
G 33
17 ^G
V ₃₂
G
18 ^V
31
19
30
20
G ₂₉
21 ^G
28
22
27
23
24* ^G
26
G ₂₅
C5 G G C6
FB = Dale ILB1206 - 300 (300:@ 100 MHz)
Cermaic Caps C3 = 10–22 PF C4 = 0.005 PF C5 = 10 PF C6 = 0.1 PF
G = VIA to GND plane layer V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1 PF ceramic
* For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3
Rev 1.0, November 20, 2006
Page 20 of 21