CY28317-2 Datasheet, PDF (2/20 Pages) Cypress Semiconductor – FTG for Mobile VIA PL133T and PLE133T Chipsets

CY28317-2
Pin Definitions
Pin Name
Pin No. Pin Type
Pin Description
CPU0, CPU1
48, 47
O
CPU Clock Output 0 through 1: CPU clocks for processor and chipset.
CPUT, CPUC
44, 43
O
Differential CPU Clock Output: Differential CPU clocks for processor.
PCI2:6
13, 14, 15,
16, 17
O
PCI Clock Outputs 2 through 6: 3.3V 33-MHz PCI clock outputs. Frequency
is set by FS0:4 inputs or through serial data interface.
PCI1/FS3
11
I/O
Fixed PCI Clock Output/Frequency Select 3: 3.3V PCI clock outputs. As an
output, the frequency is set by FS0:4 inputs or through serial data interface. This
pin also serves as a power-on strap option to determine device operating
frequency, as described in Table 6.
PCI0_F/FS4
10
I/O
Fixed PCI Clock Output/Frequency Select 4: 3.3V Free-running PCI clock
outputs. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 6.
RST#
41
O
Reset# Output: Open drain system reset output.
(open-drai
n)
48MHz/FS0
27
I/O
48 MHz Output/Frequency Select 0: 3.3V 48-MHz non-spread spectrum
output. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 6.
24_48MHz/
FS1
26
I/O
24_48MHz Output/Frequency Select 1: 3.3V 24 or 48 MHz non-spread
spectrum output. This pin also serves as a power-on strap option to determine
device operating frequency as described in Table 6.
REF1/FS2
2
I/O
Reference Clock Output 1/Frequency Select 2: 3.3V 14.318 MHz output
clock. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 6.
REF0
3
O
Reference Clock Output 0: 3.3V 14.318-MHz output clock.
SDRAMIN
18
I
SDRAM Buffer Input Pin: Reference input for SDRAM buffer.
SDRAM0:6
37, 36, 34,
O
SDRAM Outputs: These thirteen dedicated outputs provide copies of the signal
33, 31, 30, 39
provided at the SDRAMIN input.
SCLK
25
I
Clock pin for SMBus circuitry.
SDATA
24
I/O
Data pin for SMBus circuitry.
X1
7
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection or
as an external reference frequency input.
X2
8
O
Crystal Connection: An output connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
PD#
21
I
Power Down Control: LVTTL-compatible input that places the device in
power-down mode when held LOW.
CPU_STOP#
19
I
CPU Output Control: 3.3V LVTTL compatible input that stops CPU0, CPU1,
CPUT, and CPUC when held LOW.
PCI_STOP#
20
I
PCI Output Control: 3.3V LVTTL compatible input that stop PCI1:6 when held
LOW.
IREF
40
I
Current Reference Input: Current reference for differential CPU output.
MULT_SEL
22
I
CPUT and CPUC Output Control: Control the current multiplier for differential
CPU output. Set this pin LOW for 1.0V output swing and set this pin HIGH for
0.7V output swing.
VTT_PWRGD#
4
I
VTT_PWRGD#: 3.3V LVTTL compatible input that controls the FS0:4 to be
latched and enables all outputs. CY28316 will sample the FS0:4 inputs and
enable all clock outputs after all the VDD become valid and VTT_PWRGD# is
held LOW.
Rev 1.0, November 25, 2006
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