CY28346 Datasheet, PDF (15/19 Pages) Cypress Semiconductor – Clock Synthesizer with Differential CPU Outputs

CY28346
AC Parameters (V_DD = V_DDA = 3.3V ±5%, T_A = 0°C to +70°C) (continued)
66 MHz
100 MHz
133 MHz
200 MHz
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
T_CCJ
CPU Cycle to Cycle
Jitter
150
150
150
150 ps 15, 16,
19
T_R/T_F
CPUT and CPUC Rise 175 700 175 700 175 700 175 700 ps 15, 17,
and Fall Times
20
Rise/Fall Matching
20%
20%
20%
20%
17, 18,
19
DeltaT_R
DeltaT_F
V_CROSS
Rise Time Variation
125
125
125
125 ps 17, 19
Fall Time Variation
125
125
125
125 ps 17, 19
Crossing Point Voltage 280 430 280 430 280 430 280 430 mV 15, 19
at 0.7V Swing
CPU at 1.0V Timing
T_DC
CPUT and CPUC Duty 45
55
45
55
45
55
45
55 % 15, 16
Cycle
T_PERIOD
CPUT and CPUC
Period
14.85 15.3 9.85 10.2 7.35 7.65 4.85 5.1 nS 15, 16
T_SKEW
Any CPU to Any CPU
100
Clock Skew
100
100
100 pS 12, 15,
16
T_CCJ
CPU Cycle to Cycle
Jitter
150
150
150
150 pS 12, 16
Differential
T_R/T_F
SE–
DeltaSlew
CPUT and CPUC Rise 175 467 175 467 175 467 175 467 ps 15, 20
and Fall Times
Absolute Single- ended
325
Rise/Fall Waveform
Symmetry
325
325
325 ps 21, 22
V_CROSS
Cross Point at 1.0V
swing
510 760 510 760 510 760 510 760 mV 22
3V66
T_DC
T_PERIOD
T_HIGH
T_LOW
T_R/T_F
3V66 Duty Cycle
3V66 Period
3V66 HIGH Time
3V66 LOW Time
3V66 Rise and Fall
Times
45
55
45
55
45
55
45
55 % 12, 13
15.0 15.3 15.0 15.3 15.0 15.3 15.0 15.3 ns 9, 12, 13
4.95
4.95
4.95
4.95
ns 23
4.55
4.55
4.55
4.55
ns 24
0.5
2.0
0.5 2.0 0.5 2.0 0.5 2.0 ns
25
T_SKEW
Unbuffered
3V66 to 3V66 Clock
Skew
500
500
500
500 ps 12, 13
T_SKEW
Buffered
3V66 to 3V66 Clock
Skew
250
250
250
250 ps 12, 13
T_CCJ
DRCG Cycle to Cycle
250
Jitter
250
250
250 ps 12, 13
Notes:
20. Measurement taken from differential waveform, from –0.35V to +0.35V.
21. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous difference
between maximum CLK rise (fall) and minimum CLK# fall (rise) time or minimum CLK rise (fall) and maximum CLK# fall (rise) time.” This parameter is designed
form waveform symmetry.
22. Measured in absolute voltage, i.e., single-ended measurement.
23. THIGH is measured at 2.4V for non-host outputs.
24. TLOW is measured at 0.4V for all outputs.
25. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data
sheet).
Rev 1.0, November 24, 2006
Page 15 of 19