CY28439 Datasheet, PDF (14/21 Pages) SpectraLinear Inc – Clock Generator for Intel Grantsdale Chipset

CY28439
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tstable
<1.8 ms
Tdrive_PWRDN#
<300Ps >200mV
Figure 5. Power-down Deassertion Timing Waveform
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
VDD Clock Gen
Clock State State 0
0.2-0.3mS
Delay
State 1
Wait for
VTT_PW RGD#
Sample Sels
State 2
Device is not affected,
VTT_PW RGD# is ignored
State 3
Off
Clock Outputs
Off
Clock VCO
On
On
Figure 6. VTT_PWRGD# Timing Diagram
VDD_A = 2.0V
S0
Power Off
S1
Delay
>0.25 ms
VTT_PWRGD# = Low
S2
Sam ple
Inputs straps
VDD_A = off
S3
N orm al
Operation
VTT_PWRGD# = toggle
W ait for <1.8ms
Enable Outputs
Figure 7. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 21, 2006
Page 14 of 21