CY28378 Datasheet, PDF (12/21 Pages) Cypress Semiconductor – FTG for Pentium 4 and Intel 845 Series Chipset

CY28378
Table 7. Maximum Lumped Capacitive Output Loads
PCI, PCI_F
3V66
48M_24MHz, 48MHz
REF
CPUT/C
CPU_ITP
Clock
Table 8. Group Timing Relationship and Tolerances
3V66 to PCI
Offset
Typical 2.5 ns
Tolerance
(or Range)
1.5 – 3.5 ns
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
PD# – Assertion
PWRDWN#
CPUT, 133MHz
Max Load
20
30
20
30
See Figure 4
Units
pF
pF
pF
pF
pF
Conditions
3V66 leads
Notes
See Note 2
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low “stopped” state.
CPUC, 133MHz
AGP, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.131818
Figure 2. Power-down Assertion Timing Waveforms
Rev 1.0, November 20, 2006
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