CY28442 Datasheet, PDF (11/21 Pages) Cypress Semiconductor – Clock Generator for Intel Alviso Chipset

CY28442
CLK_REQ[0:1]# Description
The CLKREQ#[A:B] signals are active low input used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by CLKREQ#[A:B] are determined by the settings
in register byte 8. The CLKREQ# signal is a de-bounced signal
in that it’s state must remain unchanged during two consec-
utive rising edges of SRCC to be recognized as a valid
assertion or de-assertion. (The assertion and de-assertion of
this signal is absolutely asynchronous).
CLKREQ#X
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform
CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW)
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the assertion to active outputs is between 2-6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. All stopped SRC outputs must be driven high
within 10 ns of CLKREQ#[1:0] de-assertion to a voltage
greater than 200mV.
CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH)
The impact of deasserting the CLKREQ#[A:B] pins is all SRC
outputs that are set in the control registers to stoppable via
deassertion of CLKREQ#[A:B] are to be stopped after their
next transition. The final state of all stopped DIF signals is low,
both SRCT clock and SRCC clock outputs will not be driven.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual function pin. During initial
power up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled low by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
active high input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted high, all clocks need to be driven
to a low value and held prior to turning off the VCOs and the
crystal oscillator.
PD (Power-down) – Assertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must held high or
Tri-stated (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition within 4
clock periods. When the SMBus PD drive mode bit corre-
sponding to the differential (CPU, SRC, and DOT) clock output
of interest is programmed to ‘0’, the clock output are held with
“Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tristate. Note the example
below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all
differential outputs. This diagram and description is applicable
to valid CPU frequencies 100,133,166,200,266,333 and
400MHz. In the event that PD mode is desired as the initial
power-on state, PD must be asserted high in less than 10 uS
after asserting Vtt_PwrGd#.
Rev 1.0, November 21, 2006
Page 11 of 21