CY28409 Datasheet, PDF (11/16 Pages) Cypress Semiconductor – Clock Synthesizer with Differential SRC and CPU Outputs

CY28409
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
VDD Clock Gen
Clock State State 0
0.2-0.3 ms
Delay
State 1
Wait for
VTT_PWRGD#
Sample Sels
State 2
Device is not affected,
VTT_PWRGD# is ignored
State 3
Off
Clock Outputs
Off
Clock VCO
On
On
Figure 9. VTT_PWRGD# Timing Diagram
VDDA = 2.0V
S0
Power Off
S1
Delay
>0.25 ms
VTT_PWRGD# = Low
S2
Sample
Inputs straps
VDDA = off
S3
Normal
Operation
VTT_PWRGD# = toggle
Wait for <1.8 ms
Enable Outputs
Figure 10. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 22, 2006
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