CY2SSTU877 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer

CY2SSTU877
1.8V, 500 MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
Features
• Operating frequency: 125 MHz to 500 MHz
• Supports DDRII SDRAM
• 1 to 10 differential clock buffer (SSTL_18)
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): 40 ps
• Very low output-to-output skew: 40 ps
• Auto power-down feature when input is low
• 1.8V operation
• Fully JEDEC-compliant (JESD 82-8)
• 52-ball BGA
Functional Description
The CY2SSTU877 is a high-performance, low-skew, low-jitter
zero delay buffer designed to distribute differential clocks in
high-speed applications.
This phase-locked loop (PLL) clock buffer is designed for a
V_DD of 1.8V, an AV_DD of 1.8V and SSTL18 differential data
input and output levels. This device is a zero delay buffer that
distributes a differential clock input pair (CK, CK#) to ten differ-
ential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential
pair of feedback clock outputs (FBOUT, FBOUT#).
The input clocks (CK, CK#), the feedback clocks (FBIN,
FBIN#), the LVCMOS (OE, OS), and the analog power input
(AVDD) control the clock outputs.
The PLL in the CY2SSTU877 clock driver uses the input
clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to
provide high-performance, low-skew, low-jitter output differ-
ential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able
to track Spread Spectrum Clocking (SSC) for reduced EMI.
When AVDD is grounded, the PLL is turned off and bypassed
for test purposes. When both clock signals (CK, CK#) are logic
low, the device will enter a low-power mode. An input logic
detection circuit on the differential inputs, independent from
the input buffers, will detect the logic low level and perform a
low-power state where all outputs, the feedback, and the PLL
are OFF. When the inputs transition from both being logic low
to being differential signals, the PLL will be turned back on, the
inputs and outputs will be enabled and the PLL will obtain
phase lock between the feedback clock pair (FBIN, FBIN#)
and the input clock pair (CK, CK#) within the specified stabili-
zation time t_L.
Block Diagram
Pin Configuration
1
2
3
4
5
6
A CLKT1 CLKT0 CLKC0 CLKC5 CLKT5 CLKT6
B CLKC1 GND GND GND GND CLKC6
C CLKC2 GND
NB
NB
GND CLKC7
D CLKT2 VDDQ VDDQ VDDQ OS CLKT7
E CLK_INT VDDQ NB
NB VDDQ FB_INT
F CLK_INC VDDQ NB
NB
OE FB_INC
G
AGND VDDQ VDDQ VDDQ VDDQ FB_OUTC
H
AVDD GND
NB
NB
GND FB_OUTT
J
CLKT3 GND
GND
GND GND CLKT8
K CLKC3 CLKC4 CLKT4 CLKT9 CLKC9 CLKC8
52 BGA
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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