CY28RS480 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – Clock Generator for ATI RS480 Chipset

CY28RS480
Clock Generator for ATI^£ RS480 Chipset
Features
• Supports AMD^£ CPU
• 200 MHz differential CPU clock pairs
• 100 MHz differential SRC clocks
• 48 MHz USB clock
• 33 MHz PCI clock
• 66 MHz HyperTransport¥ clock
Block Diagram
XIN
XOUT
CPU_STP#
CLKREQ[0:1]#
XTAL
OSC
PLL Ref Freq
PLL1
Divider
Network
IREF
PD
PLL2
SDATA
SCLK
I²C
Logic
• I²C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU SRC HTT66 PCI
x2
x8
x1
x1
REF USB_48
x3
x1
Pin Configuration
VDD_REF
REF[0:2]
VDD_CPU
CPUT[0:1], CPUC[0:1],
VDD_SRC
SRCT[0:5],SRCC[0:5]
VDD_SRCS
SRCST[0:1],SRCSC[0:1]
VDD_PCI
PCI
VDD_HTT
HTT66
VDD_48 MHz
USB_48
XIN
XOUT
VDD_48
USB_48
VSS_48
NC
SCLK
SDATA
NC
CLKREQ#0
CLKREQ#1
SRCT5
SRCC5
VDD_SRC
VSS_SRC
SRCT4
SRCC4
SRCT3
SRCC3
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
SRCST1
SRCSC1
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
56 SSOP/TSSOP
VDD_REF
VSS_REF
REF0
REF1
REF2
VDD_PCI
PCI0
VSS_PCI
VDD_HTT
HTT66
VSS_HTT
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
VDDA
VSSA
IREF
VSS_SRC1
VDD_SRC1
SRCT0
SRCC0
VDD_SRCS
VSS_SRCS
SRCST0
SRCSC0
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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