CY28410-2 Datasheet, PDF (1/16 Pages) SpectraLinear Inc – Clock Generator for Intel Grantsdale Chipset

CY28410-2
Clock Generator for Intel^£ Grantsdale Chipset
Features
• Compliant with Intel^£ CK410
• Supports Intel P4 and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• 33-MHz PCI clock
• Low-voltage frequency select input
• I²C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU
SRC
PCI
x2 / x3
x6 / x7
x9
REF
x1
DOT96
x1
USB_48
x1
Block Diagram
XIN
XOUT
FS_[C:A]
VTT_PWRGD#
IREF
XTAL
OSC
PLL Ref Freq
PLL1
Divider
Network
PD
PLL2
SDATA
SCLK
I²C
Logic
Pin Configuration
VDD_REF
REF
VDD_PCI
VSS_PCI
VDD_CPU
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
VDD_SRC
SRCT[1:6], SRCC[1:6]
PCI3
PCI4
PCI5
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
PCIF1
VDD_PCI
PCI[0:5]
PCIF2
VDD_48
VDD_PCIF
USB_48
PCIF[0:2]
VSS_48
DOT96T
VDD_48 MHz
DOT96C
FS_B/TEST_MODE
DOT96T
DOT96C
USB_48
VTT_PWRGD#/PD
FS_A
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
SRCT3
SRCC3
SRC4-SATAT
SRC4_SATAC
VDD_SRC
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
56 SSOP/TSSOP
PCI2
PCI1
PCI0
FS_C/TEST_SEL
REF
VSS_REF
XIN
XOUT
VDD_REF
SDATA
SCLK
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
VSSA
VDDA
CPUT2_ITP/SRCT7
CPUC2_ITP/SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
SRCC5
VSS_SRC
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 16
www.SpectraLinear.com